The present invention relates generally to semiconductor packaging, and more specifically, to a substrate having embedded wires for providing electrical inter-connection within an integrated circuit package.
Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as xe2x80x9cdiesxe2x80x9d, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. For this purpose, many types of packaging have been developed, including xe2x80x9cflip-chipxe2x80x9d, ball grid array and leaded grid array among other mounting configurations. These configurations typically use a planar printed circuit etched on the substrate with bonding pads and the connections to the die are made by either wire bonding or direct solder connection to the die.
The resolution of the printed circuit is often the limiting factor controlling interconnect density. Photo-etch and other processes for developing a printed circuit on a substrate have resolution limitations and associated cost limitations that set the level of interconnect density at a level that is less than desirable for interfacing to present integrated circuit dies that may have hundreds of external connections.
As the density of circuit traces interfacing an integrated circuit die are increased, the inter-conductor spacing must typically be decreased. However, reducing inter-conductor spacing has a disadvantage that migration and shorting may occur more frequently for lowered inter-conductor spacing, thus setting another practical limit on the interconnect density.
The above-incorporated patent applications xe2x80x9cINTEGRATED CIRCUIT SUBSTRATE HAVING LASER-EMBEDDED CONDUCTIVE PATTERNS AND METHOD THEREFORxe2x80x9d and xe2x80x9cIMPRINTED INTEGRATED CIRCUIT SUBSTRATE AND METHOD FOR IMPRINTING AN INTEGRATED CIRCUIT SUBSTRATExe2x80x9d describe novel circuit substrates that embed conductive patterns beneath the surface of a printed circuit substrate, thus reducing susceptibility to migration and shorting between the conductors.
However, the techniques described in the above-referenced patent applications use plating and etching processes and otherwise have all of the limitations and disadvantages associated with printed circuit technology.
Therefore, it would be desirable to provide a method and substrate having further increased interconnect density with a low associated manufacturing cost. It would further be desirable to provide a method and substrate that prevents shorting and migration between conductors. It would also be desirable to provide a method and substrate that do not require an etching or plating process.
A substrate having embedded wires forming conductive patterns within a substrate and a method for manufacturing generate a circuit pattern within a substrate having wires embedded beneath the surface of the substrate. A substantially planar metal layer is covered with a dielectric material and multiple conductive wires are laid in a plane parallel to the metal layer to form the conductive pattern for interconnecting circuits mounted to the substrate and terminals for external connections. The wires and/or the dielectric are heated to secure the wires in position by partial flow of the dielectric material and subsequently covered by another layer of dielectric.
Upwardly-projecting wire stubs may be bonded to the metal layer to provide attachment points for wires, thus providing blind via connections to the metal layer. Holes may be drilled or etched in the metal layer to provide voids for the passage of through vias. The holes are filled with an epoxy and epoxy-filled openings are then laser-ablated, plasma etched or chemically etched to form via paths that are subsequently filled with a conductive material. Upwardly-projecting wire stubs may also be bonded to the conductive material to connect the conductive pattern to the through vias. Multiple layers and double-sided substrates may be provided by adding additional dielectric and conductive wire layers.